The following copending, commonly assigned U.S. patent applications contain disclosure pertinent to the present inventions: Ser. No. 09/138,858, filed Aug. 24, 1998; Ser. No. 08/440,665 filed May 15, 1995, now U.S. Pat. No. 5,801,441; Ser No. 08/271,768, filed on Jul. 7, 1994, now U.S. Pat. No. 5,518,964; Ser. No. 09/095,251, filed Jun. 10, 1998; Ser. No. 08/532,528 filed Sep. 22, 1995, now U.S. Pat. Nos. 5,798,286; and Ser. No. 08/690,532 filed Jul. 31, 1996. The disclosures of said applications and patents are incorporated by reference herein. The disclosure of U.S. Pat. No. 5,148,266 is also incorporated by reference herein.
A copending, commonly assigned U.S. patent application entitled Framed Sheet Processing, which application claims benefit of said U.S. Provisional Patent Application No. 60/061,932 is being filed of even date herewith. Said application filed of even date herewith is hereby incorporated by reference herein.
The present invention relates to fabrication of microelectronic circuit components, interconnections and packages, and to articles useful in such processes.
Many microelectronic assemblies employ panel-like circuit elements. For example, one common method of connecting the contacts on a semiconductor chip to external circuitry, referred to as tape automated bonding or “TAB” uses a sheet-like tape including a flexible dielectric layer, typically polyimide with metallic circuit traces thereon. Ordinarily, these circuit traces are formed by photochemical processes such as etching or plating using photographically patterned resists. The precision with which such a circuit can be formed is limited by the dimensional stability of the dielectric layer during processing. This problem increases as the size of the circuit increases. Typical TAB tape has numerous individual circuits made by photographically patterning an area of the flexible circuit of the size required to mount a single chip. The individual circuits are spaced along the length of the chip. Because the process only requires registration of features over a relatively small region corresponding to the dimensions of an individual chip, there is no need to maintain precise spacing between widely separated features. Moreover, typical TAB tapes do not require especially precise registration between features formed in different stages of the manufacturing process.
Larger circuits which require precise relative location of widely-spaced features have been fabricated heretofore using a “decal” or “applique” approach in which the flexible circuit is fabricated on the surface of a metallic plate. The metallic plate is then removed, as by exposure to a caustic etching process. For example, certain embodiments of U.S. Pat. No. 5,055,907 disclose manufacture of a large circuit on the surface of an aluminum plate. After fabrication of the circuit, and after microelectronic elements such as individual semiconductor chips are mounted to the circuit, a support ring is attached around the periphery of the circuit and the plate is removed. In this arrangement, the plate maintains dimensional stability of the circuit throughout the fabrication and mounting process. However, the additional process steps required to remove the plate considerably complicate use of this approach. Also, the plate precludes access to one side of the circuit which impedes the fabrication process and restricts the design of the finished product.
The aforementioned U.S. Pat. No. 5,518,964 and the corresponding PCT International Publication WO 96/02068, the disclosure of which is also hereby incorporated by reference herein, disclose processes in which circuit elements such as microelectronic connection components are fabricated in the form of a wafer-size sheet. In certain processes disclosed in the '964 patent, a sheet of a starting material such as a flexible dielectric sheet with metallic layers thereon is stretched and bonded to a rigid frame having an opening or aperture therein so that the sheet is held taut by the rigid frame and maintained under tension by the frame. The frame may be in the form of a ring. The ring may be formed from a material such as molybdenum, which has a coefficient of thermal expansion close to that of a silicon semiconductor wafer, and lower than the coefficient of expansion of the sheet. The sheet may be stretched and attached as by bonding to the ring at an elevated temperature, so that the sheet remains in tension during processing at lower temperatures. While the sheet is held in the ring, it is accessible from both sides. The sheet is treated using various circuit-fabrication techniques such as etching and plating using photographically patterned resists. Because the sheet is maintained under tension throughout the process, it remains dimensionally stable. Because the sheet is accessible from both sides, fabrication of the sheet, and mounting of the sheet to the wafer can be performed readily. The features formed on the sheet are precisely positioned relative to one another over the entire extent of the sheet.
After processing, the entire sheet, with the rings still attached, can be aligned with a large assemblage of semiconductor chips such as a unitary semiconductor wafer. Leads formed during the fabrication process can be connected to all of the chips on the wafer. After connection, and after other processes such as deformation of leads on the sheet and injection of curable compliant material, the individual chips and associated portions of the sheet can be severed to provide individual packaged chips or subassemblies, each including one or more chips and an associated part of the sheet. Thus, the basic approach of using a rigid frame around the periphery of a sheet to provide dimensional stability during fabrication, as set forth in the '964 patent, allows fabrication of microelectronic circuit elements in large array, such as wafer-size arrays with excellent dimensional stability and control. Further improvements in this basic approach are taught in the aforementioned commonly assigned U.S. patent application Ser. No. 08/690,532 filed Jul. 31, 1996, entitled Fixtures And Methods Of Lead Bonding and Deformation. In certain preferred embodiments taught in the '532 application, the sheet may be stretched by initially attaching it to a ring formed from a material of relatively high coefficient of thermal expansion such as aluminum at a low temperature such as room temperature, then heating the sheet and high-expansion ring and then attaching the sheet to a lower expansion ring such a molybdenum ring. As disclosed, for example, in said U.S. Pat. No. 5,798,286 and in the corresponding PCT International Publication WO 97/11486, the disclosure of which is also hereby incorporated by reference herein, a frame-stretched sheet can be used in other assembly processes using individual semiconductor chips mounted individually to the sheet or mounted on a platen in a preselected array and bonded to the sheet as a unit.
Framed sheets have also been employed in unrelated arts and for different purposes. For example, thin framed sheets referred to as pellicles used in the optical arts as optical beam splitters as shown, for example, in Edmund Scientific, 1997 Optics and Optical Instruments Catalog, p. 56. U.S. Pat. No. 4,037,111 discloses the use of a mechanically stretched sheet held taut by a borosilicate glass frame as a mask for X-ray lithography. German Offenlegungssachrift DE-3,919,564 A1 discloses fabrication of printed circuits by silk-screening onto a polyimide film held taut by an aluminum frame.
U.S. Pat. Nos. 3,537,169; 5,288,663; 5,169,804; 5,654,204; 3,562,058 and 5,362,681 teach processes in which a wafer is adhered to a plastic film or “dicing tape,” then sawn into individual chips, whereupon the resulting chips are released from the film. In certain processes described in these patents, the film is carried by a frame.
U.S. Pat. No. 5,622,900 discloses a method in which a wafer is sawn into individual chips prior to completion of fabrication steps. Before sawing, the back side of the wafer is bonded to a “dicing tape” held on an opaque, aluminum ring. A UV-transparent “substrate wafer” is bonded to the side of the tape opposite from the wafer to be processed. The substrate wafer holds the individual chips in position after sawing. After processing is complete, the assembly is exposed to ultraviolet light through the transparent substrate wafer.
U.S. Pat. No. 5,605,844 discloses a system in which a dicing sheet or film is bonded to a ring of unspecified composition and a wafer is bond to the dicing sheet and sawn into individual chips. After dicing, while the individual chips are still retained on the dicing sheet, the chips are engaged with a tester or “contactor” so that features on the contactor engage features of the chips and/or engage in the kerfs between chips left by the sawing operation. The engaged contactor and chips are then subjected to a burn-in operation at an elevated temperature. As the temperature of the assembly changes, the chips move with the features of the contact and the sheet stretches to accommodate such movement.
Despite all of these improvements and efforts in the art, still further improvements would be desirable.